The present invention relates to a technology applying built-in self-testing (BIST) and a computer program for executing the method.
In recent years, as a method of designing semiconductor integrated circuits such as LSIs or ASICs, attention has been focused on a technique for describing a configuration of a logic circuit as a target to be designed using a hardware description language (xe2x80x9cHDLxe2x80x9d) and configuring the logic circuit as a combination of respective circuit elements based on this description. In this kind of technique, a circuit configuration is described in the HDL at a register transfer level (xe2x80x9cRTLxe2x80x9d), and this description is given to a logic synthesizing tool to synthesize logic, and a desired circuit is formed. The logic circuit configured in the above manner is subjected to optimization processing relating to its timing and area to obtain a final logic circuit.
At present, it has become common that design for testability (DFT) is adopted in design of the logic circuit using such an HDL based on the idea that testing is taken into account in a designing stage. This is a design technique for providing an additive circuit so as to improve observability and controllability of an inner side of the circuit so that testing the circuit becomes easier. Of the techniques for design for testability, attention is given to the built-in self-test (BIST) in which a BIST circuit is built-in, inside the LSI, because the circuit can efficiently perform tests with comparatively low cost.
Logic BIST as one of the BISTs has been widely accepted in the field of logic circuit design, and a test function effective in components, boards, and system test is provided. Software for supporting design based on the logic BIST generally has a system mode as an operation mode in actual use and a logic BIST mode as a built-in self-test circuit operation mode. The logic BIST mode is an integrated built-in automatic test mode for automatically creating, inserting, and verifying full scan of logic and the built-in self-test circuit.
That is, in the logic BIST mode, a BIST circuit, such as an LFSR (Line Feedback Shift Register) or an MISR (Multiple Input Signature Register), is automatically created, and in order to perform full scan, a flip flop (hereafter abbreviated as FF) that originally performs a temporary storage function is included with a selector as shown in FIG. 10, that is, a scan flip flop (hereafter abbreviated as SFF). A plurality of scan paths connect the flip flops in series using the selectors so that the flip flops can be freely connected to or separated from each other through combinational circuits or the like.
As shown in FIG. 10, the SFF 100 includes the FF 101 that performs a temporary storage function using an original clock signal as a trigger signal, and the selector 102 of the previous stage. The selector 102 selects a signal D from the combinational circuit in the previous stage when a scan mode signal SM is 0. At this time, the respective SFFs 100 are separated from each other, and the FF 101 performs functions as the main body of the FF of synchronizing to the clock signal CLK and transferring the signal D from the combinational circuit in the previous stage to a combinational circuit in the subsequent stage as output OUT.
On the other hand, when the scan mode signal SM is 1, the selector 102 selects a signal SI from the SFF in the previous stage. Accordingly, the SFFs 100 are cascade-connected to each other, and the FF 101 synchronizes to the clock signal CLK, and transfers the output signal of the SFF in the previous stage as output SO to the SFF in the subsequent stage.
In the design into which such a logic BIST is introduced, it is required to consider timing restrictions in an actual speed in both the system mode and the logic BIST mode. However, giving the timing restrictions to both of the modes reduces the convergence of its layout and increases the area and power consumption due to increase in the number of gates. However, optimization of timing to the system mode and the logic BIST mode is impossible in the current logic synthesizing tool.
Therefore, conventionally, as shown in FIG. 11, optimization of timing in the system mode is previously performed (step S100), a timing error in the system mode is first eliminated, and timing verification is then performed in the logic BIST mode (step S101).
However, paths used for the system mode and the logic BIST mode are different, so that timing restrictions to the paths are also different. Since optimization of the timing is performed in the system mode, a timing error does not occur in the system mode, but it may occur in the logic BIST mode. That is, as shown in FIG. 12A, when fixing of input data DATA to the FF satisfies a setup time ST, a timing error will not occur. However, as shown in FIG. 12B, if a path delay between the SFFs exceeds the timing restriction, for example, if the clock signal CLK input to the FF changes from 0 to 1 before the input data DATA to the FF is fixed, the fixing does not satisfy the setup time ST for the FF, so that a timing error will occur.
Therefore, conventionally, timing analysis is performed in the logic BIST mode, and when a timing error occurs, the SFF on the sending side of a position where the timing error has occurred is replaced by a multi-cycle path-capable scan flip flop MSFF as shown in FIG. 13A (step S102 in FIG. 11).
As shown in FIG. 13B, in the multi-cycle path-capable scan flip flop MSFF, scan data SD is selected when a clock enable signal CE is 1, and output Q1 of the flip flop FF is selected when the CE is 0. When a scan enable signal SE is 1, the mode is changed to scan mode for the logic BIST. When the SE is 1 and CE is 1, the SD is output to the Q1. When the SE is 1 and the CE is 0, output of the FF is looped and the same data is input. Therefore, the clock signal CLK to be input to the FF seems to be stopped. If the output Q1 of the multi-cycle path-capable scan flip flop MSFF on the sending side is looped until a data signal DAT2 is fixed and the SE is made to 0 after the DAT2 is fixed, the DAT2 is selected and output to the Q2.
FIG. 14 shows a time chart of the multi-cycle path-capable scan flip flop MSFF. When the clock enable signal CE is 0, the output of the FF is looped. Therefore, by giving a signal having a cycle twice as long as the CLK to the CE, the FF seems to operate in two cycles. Further, when the scan enable signal SE is 0, the CE is left to 0 as it is. When the FF is operated in one cycle, the SE is made to 0 at the first cycle. Therefore, when there is a delay by one cycle or longer for fixing the value of the DAT2, the fixing does not satisfy the setup time ST, so that a timing error occurs. However, when the FF is operated in two cycles, the SE can be made to 0 at the second cycle, and the value of the DAT2 has already been fixed by this time, therefore, the timing error can be avoided.
Conventionally, a timing error in the logic BIST mode is avoided by loosening timing restrictions by replacing the SFF with the multi-cycle path-capable scan flip flop MSFF to stop the clock signal until the data is fixed. Therefore, any path passing through the multi-cycle path-capable scan flip flop MSFF operates based on a clock signal CLK with a long cycle. Thus, the path related to the multi-cycle path-capable scan flip flop MSFF does not operate at actual speed. Accordingly, when the circuit is operated at actual speed in the conventional art, a timing error may occur.
It is an object of this invention to obtain a method of designing logic circuit that allows tests operated at an actual speed in both the system mode and the logic BIST mode so that a timing error can be avoided without fail. It is another object of this invention to provide a computer program that contains instructions which when executed on a computer realizes the method according to the present invention on the computer.
The method of designing logic circuit according to one aspect of this invention, is a method of designing logic circuit using a program having a system mode and a logic BIST mode. This method comprises the steps of: adjusting timing in the system mode during logic synthesis and layout; executing timing analysis in the logic BIST mode after the timing is adjusted; and inserting a scan flip flop with a selector, which includes a scan flip flop and a selector that can select output of the scan flip flop and input to the scan flip flop, into a position where a timing error has occurred based on the result of the timing analysis.
The computer program according to the another aspect of this invention contains instructions which when executed on a computer realizes the method according to the present invention on the computer. Thus, the method according to the present invention can be easily and automatically realized on the computer.
Other objects and features of this invention will become apparent from the following description with reference to the accompanying drawings.